Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory element, such as a flash memory unit. In this regard, one conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric element that is capable of storing two bits of data. In such an arrangement, one bit can be stored using a first charge storing region on one side of the charge trapping dielectric element, while a second bit can be stored using a second charge storing region on the other side of the charge trapping dielectric element.
FIG. 1 is a cross sectional view of a conventional dual bit memory cell 100. Memory cell 100 includes a silicon nitride layer 102 and a P-type semiconductor substrate 104 having a first buried junction region 106 and a second buried junction region 108. First buried junction region 106 and second buried junction region 108 are each formed from an N+ semiconductor material. Silicon nitride layer 102 is sandwiched between two layers of silicon oxide (identified by reference numbers 110 and 112).
Overlying silicon oxide layer 110 is a polysilicon gate 114. Gate 114 is doped with an N-type impurity (e.g., phosphorus). Memory cell 100 is capable of storing two data bits: a left bit represented by the dashed circle 116; and a right bit represented by the dashed circle 118. In practice, memory cell 100 is generally symmetrical and first buried junction region 106 and second buried junction region 108 are interchangeable. In this regard, first buried junction region 106 may serve as the source region with respect to the right bit 118, while second buried junction region 108 may serve as the drain region with respect to the right bit 118. Conversely, second buried junction region 108 may serve as the source region with respect to the left bit 116, while first buried junction region 106 may serve as the drain region with respect to the left bit 116.
FIG. 2 is a simplified diagram of a plurality of dual bit memory cells arranged in accordance with a conventional virtual ground array architecture 200 (a practical array architecture can include up to millions of dual bit memory cells). Array architecture 200 includes a number of buried bitlines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (reference numbers 202, 204, and 206), each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of wordlines that are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four wordlines (reference numbers 208, 210, 212, and 214) that generally form an orthogonal pattern with the bitlines. Although not shown in FIG. 2, charge trapping dielectric material is under the wordlines and between the bitlines. The dashed lines in FIG. 2 represent two of the dual bit memory cells in array architecture 200: a first cell 216 and a second cell 218. Notably, bitline 204 is shared by first cell 216 and second cell 218. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected bitline and there need not be any bitlines with a fixed ground potential.
Control logic and circuitry for array architecture 200 governs the selection of memory cells, the application of voltage to the wordlines, and the application of voltage to the bitlines during conventional flash memory operations, such as: programming; reading; erasing; soft programming; and verification. Voltage is delivered to the bitlines using conductive metal lines and bitline contacts. FIG. 2 depicts three conductive metal lines (reference numbers 220, 222, and 224) and three bitline contacts (reference numbers 226, 228, and 230). For a given bitline, a bitline contact is used once every certain number of wordlines (typically every 16 wordlines, but sometimes every 8 or every 32 wordlines).
Programming of memory cell 100 can be accomplished by known hot electron injection techniques (also known as channel hot electron or CHE programming). In accordance with conventional programming techniques, the right bit 118 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to first buried junction region 106 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to second buried junction region 108 (which serves as the drain in this case). Conversely, the left bit 116 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to second buried junction region 108 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to first buried junction region 106 (which serves as the drain in this case).
Erasing of memory cell 100 can be accomplished using hot hole erase techniques. Hot hole erasing of the left bit 116 is performed by applying a relatively high negative erase voltage (e.g., −6.0 volts) to gate 114 via the appropriately selected wordline, applying a relatively high drain bias voltage (e.g., 5.0 volts) to the bitline corresponding to first buried junction region 106 (which serves as the drain in this scenario), and floating the bitline corresponding to second buried junction region 108 (which serves as the source in this scenario). Hot hole erasing of the right bit 118 is performed by applying a relatively high negative erase voltage (e.g., −6.0 volts) to gate 114 via the appropriately selected wordline, applying a relatively high drain bias voltage (e.g., 5.0 volts) to the bitline corresponding to second buried junction region 108 (which serves as the drain in this scenario), and floating the bitline corresponding to first buried junction region 106 (which serves as the source in this scenario). Such erasing is intended to leave both bits of memory cell 100 in an erased or unprogrammed state. Flash memory arrays typically include sectors of many individual memory cells, and the cells are typically erased on a sector-by-sector basis. In other words, all of the bits in a given sector are erased before the erase operation proceeds to the next sector.
Conventional hot hole erasing of flash memory cells utilizes defined and fixed erase bias voltages (i.e., the negative gate voltage and the drain bias voltage are fixed during the erase procedure and throughout the entire life of the flash memory device). These fixed voltages are selected to compensate for the effects of program-erase cycling, which alters the electrical characteristics of the memory cells over time. In this regard, memory cells that have been highly cycled typically require higher negative gate voltage and/or higher drain voltage during erase operations, relative to memory cells that have been subjected to less cycling. Thus, the fixed erase bias voltages are selected to accommodate the “worst case scenario” of highly cycled cells. Although relatively high drain voltage and/or relatively high negative gate voltage may be desirable to erase highly-cycled memory cells, such bias voltages may not be necessary to erase memory cells that have not been highly cycled. Indeed, the application of very high negative gate voltage and/or very high drain voltage during an erase operation on newer devices can induce degradation in the memory cells. On the other hand, if relatively lower negative gate bias and/or relatively low drain voltage is used to minimize degradation, the erase time for highly cycled devices will be too long.